Signals and Systems

10.8 System Function Algebra and Block Diagrams

Imron Rosyadi

10.8 System Function Algebra and Block Diagram Representations

In this section, we’ll see how the Z-transform simplifies the representation and analysis of interconnected LTI systems. Just as with the Laplace transform, it allows us to replace complex time-domain operations with simple algebraic manipulations. This is especially useful for understanding feedback systems and for designing practical implementations of digital filters using block diagrams.

10.8.1 System Functions for Interconnections of LTI Systems

Power of Z-Transform:

• Replaces time-domain operations (convolution, time shifting) with algebraic operations.
• Simplifies analysis of complex system interconnections.

Common Interconnections:

1. Series/Cascade: If \(H_1(z)\) and \(H_2(z)\) are cascaded, the overall system function is: \[ H(z) = H_1(z)H_2(z) \]
2. Parallel: If \(H_1(z)\) and \(H_2(z)\) are in parallel, the overall system function is: \[ H(z) = H_1(z)+H_2(z) \]
3. Feedback: For the feedback system shown in Figure 10.17, the overall system function is: \[ H(z)=\frac{Y(z)}{X(z)}=\frac{H_{1}(z)}{1+H_{1}(z) H_{2}(z)} \]

One of the greatest advantages of the Z-transform is its ability to simplify the analysis of interconnected LTI systems. Instead of dealing with complex convolutions in the time domain, we can use simple algebraic operations in the Z-domain.

This slide summarizes the system function algebra for series, parallel, and feedback interconnections. The derivation for the feedback system highlights how algebraic manipulation makes the analysis straightforward, leading to a closed-form expression for the overall system function. This is critical for understanding control systems and feedback loops.

10.8.2 Block Diagram Representations for Causal LTI Systems

Basic Building Blocks:

Causal LTI systems described by difference equations can be represented using three fundamental operations:

1. Adder: Sums two or more signals.
2. Coefficient Multiplier: Multiplies a signal by a constant.
3. Unit Delay (\(z^{-1}\)): Delays a signal by one sample (\(y[n]=x[n-1]\)).

10.8.2 Block Diagram Representations for Causal LTI Systems

Example 10.28: First-Order System

\(H(z)=\frac{1}{1-\frac{1}{4} z^{-1}}\)

Difference Equation: \(y[n] - \frac{1}{4}y[n-1] = x[n]\)

Rearrange for \(y[n]\): \(y[n] = x[n] + \frac{1}{4}y[n-1]\)

Equivalence to Feedback Form:

The block diagram for \(H(z)=\frac{1}{1-\frac{1}{4} z^{-1}}\) can be seen as a feedback system where:

• \(H_1(z) = 1\) (the forward path)
• \(H_2(z) = -\frac{1}{4}z^{-1}\) (the feedback path)

Applying the feedback formula: \[ H(z) = \frac{1}{1 - (1)(-\frac{1}{4}z^{-1})} = \frac{1}{1+\frac{1}{4}z^{-1}} \] Wait, this is \(1/(1+1/4 z^{-1})\). The example text stated \(H_2(z) = -1/4 z^{-1}\) for \(H(z) = 1/(1 - 1/4 z^{-1})\). Let’s recheck the formula.

10.8.2 Block Diagram Representations for Causal LTI Systems

Corrected Feedback formula application:

If \(H_1(z)\) is in the forward path and \(H_2(z)\) is in the feedback path with a negative sign at the summing junction, the formula is \(\frac{H_1(z)}{1+H_1(z)H_2(z)}\).

If the summing junction is positive, the formula is \(\frac{H_1(z)}{1-H_1(z)H_2(z)}\).

In Figure 10.18(a), the feedback is positive, so \(y[n] = x[n] + (1/4)y[n-1]\).

So \(H_1(z)=1\) (from \(x[n]\) to \(y[n]\) if no feedback) and \(H_2(z) = (1/4)z^{-1}\) (from \(y[n]\) to \(y[n-1]\) to input).

Then \(H(z) = \frac{1}{1 - (1)(1/4 z^{-1})} = \frac{1}{1 - 1/4 z^{-1}}\). This matches!

The block diagram is a direct visual representation of the difference equation.

Block diagrams are essential for visualizing and implementing discrete-time systems. They break down a system into its fundamental operations: addition, scaling, and delay. The unit delay element (\(z^{-1}\)) is particularly important as it represents memory in the system.

This example shows how a simple first-order system described by a difference equation can be directly translated into a block diagram. We also verified its equivalence to a feedback system using the Z-transform algebra, which reinforces the connection between time-domain equations and Z-domain analysis.

Example 10.29: Efficient Block Diagram for \(H(z)=\frac{1-2 z^{-1}}{1-\frac{1}{4} z^{-1}}\)

System Function: \[ H(z)=\frac{1-2 z^{-1}}{1-\frac{1}{4} z^{-1}} = \left(\frac{1}{1-\frac{1}{4} z^{-1}}\right)\left(1-2 z^{-1}\right) \] This can be seen as a cascade of two systems:

1. \(H_A(z) = \frac{1}{1-\frac{1}{4} z^{-1}}\) (from Ex. 10.28)
2. \(H_B(z) = 1-2 z^{-1}\)

Example 10.29: Efficient Block Diagram for \(H(z)=\frac{1-2 z^{-1}}{1-\frac{1}{4} z^{-1}}\)

Initial Cascade Diagram (Less Efficient):

This diagram has two separate \(z^{-1}\) blocks, both receiving \(v[n]\) as input.

Efficient Block Diagram (Direct Form II):

• Observe that the input to both unit delay elements in the initial cascade is \(v[n]\).
• The outputs of these delays (\(v[n-1]\)) are identical.
• We can share a single delay element.

Explanation:

• The first part (feedback loop) generates the intermediate signal \(v[n]\), which is the output of \(1/(1-\frac{1}{4}z^{-1})\).
• The output of the delay \(Z1\) is \(v[n-1]\).
• The final output \(y[n]\) is \(v[n] - 2v[n-1]\), which is the output of \((1-2z^{-1})\).
• This form requires fewer delay elements (memory) and is called Direct Form II.

This example illustrates an important concept in block diagram realization: efficiency. By recognizing that common signals can be shared, we can reduce the number of delay elements, which translates to less memory and computational cost in a practical implementation.

The initial cascade diagram is valid but redundant. By rearranging the order of operations and sharing the delay, we arrive at the Direct Form II realization, which is more efficient. This optimization is crucial for implementing digital filters on hardware.

Example 10.30: Second-Order System Realizations

System Function: \[ H(z)=\frac{1}{\left(1+\frac{1}{2} z^{-1}\right)\left(1-\frac{1}{4} z^{-1}\right)}=\frac{1}{1+\frac{1}{4} z^{-1}-\frac{1}{8} z^{-2}} \] Difference Equation: \(y[n] + \frac{1}{4}y[n-1] - \frac{1}{8}y[n-2] = x[n]\)

Rearrange: \(y[n] = x[n] - \frac{1}{4}y[n-1] + \frac{1}{8}y[n-2]\)

1. Direct Form I:

• Coefficients directly from the difference equation.
• Uses \(N\) delays for input terms and \(N\) delays for output terms (if \(M=N\)).

2. Cascade Form:

Factor \(H(z)\) into simpler first-order systems: \[ H(z)=\left(\frac{1}{1+\frac{1}{2} z^{-1}}\right)\left(\frac{1}{1-\frac{1}{4} z^{-1}}\right) \]

• Each factor realized as a Direct Form I or II.
• Connect them in series.

For higher-order systems, there are multiple ways to represent them using block diagrams. This example shows two common forms for a second-order system.

Direct Form I is a straightforward translation of the difference equation. It’s easy to derive but can be inefficient in terms of delay elements if there are both feedforward and feedback terms.

Cascade Form involves factoring the system function into a product of simpler (often first-order) system functions. Each simpler system is then realized, and these realizations are connected in series. This can improve numerical stability for certain implementations.

Example 10.30: Second-Order System Realizations (Continued)

3. Parallel Form:

Use partial-fraction expansion to decompose \(H(z)\): \[ H(z)=\frac{\frac{2}{3}}{1+\frac{1}{2} z^{-1}}+\frac{\frac{1}{3}}{1-\frac{1}{4} z^{-1}} \]

• Each term realized as a simpler system.
• Connect them in parallel, then sum their outputs.

Example 10.30: Second-Order System Realizations (Continued)

Example 10.31: Direct Form II (General Case)

For a general rational \(H(z)\):

\[ H(z)=\frac{\sum_{k=0}^{M} b_{k} z^{-k}}{\sum_{k=0}^{N} a_{k} z^{-k}} \]

The Direct Form II realization (which is usually more efficient than Direct Form I in terms of delay elements) is constructed by:

1. Realizing the denominator (poles) first using feedback.
2. Then realizing the numerator (zeros) using feedforward taps from the internal delayed signal.

Continuing with the second-order system, the Parallel Form is derived using partial-fraction expansion. This decomposes the system into a sum of simpler systems, which are then realized in parallel. This form can also offer numerical advantages, particularly in terms of reducing coefficient sensitivity.

Finally, the Direct Form II is a highly efficient realization for general rational system functions. It combines the feedback structure (for the denominator) and the feedforward structure (for the numerator) in a way that minimizes the number of delay elements. This is often the preferred form for digital filter implementations due to its memory efficiency.

Practical Considerations for Block Diagrams

Multiple Realizations:

• For a given \(H(z)\), there are often many possible block diagram realizations (e.g., Direct Form I, Direct Form II, Cascade, Parallel).
• All represent the same mathematical system.

Differences in Practice:

When implementing these systems on digital hardware (e.g., microcontrollers, FPGAs, DSPs):

• Finite Word Length: Coefficients must be quantized to finite precision.
• Numerical Roundoff: Arithmetic operations introduce errors.
• Coefficient Sensitivity: Different structures are more or less sensitive to quantization errors in their coefficients.
• Numerical Stability: Different structures can behave differently with respect to accumulation of roundoff errors, potentially leading to instability or inaccurate results.

Note

The choice of block diagram realization is a critical design decision in digital signal processing, impacting performance, cost, and accuracy.

Practical Considerations for Block Diagrams

Example: Direct Form I vs. Direct Form II

• Direct Form I: Requires \(N+M\) delay elements.
• Direct Form II: Requires \(\max(N,M)\) delay elements.
  • Often preferred for its memory efficiency.

Example: Cascade vs. Parallel

• Breaking down a high-order filter into a cascade or parallel of lower-order filters can improve numerical stability.
• Quantization errors in pole/zero locations can be less critical in these forms.

Active Research Area:

Considerable research in digital signal processing focuses on:

• Optimal realization structures.
• Minimizing quantization noise.
• Ensuring numerical stability under finite-precision arithmetic.

While all the block diagram forms we’ve discussed are mathematically equivalent, their practical implementation can vary significantly. This is due to the realities of digital hardware, where numbers are represented with finite precision.

Finite word length and numerical roundoff are unavoidable issues. Different block diagram structures respond differently to these limitations, affecting the accuracy and stability of the implemented system. For instance, Direct Form II is generally more memory-efficient than Direct Form I. Cascade and parallel forms can offer better numerical stability for higher-order filters.

Understanding these trade-offs is crucial for practical ECE applications, as the choice of realization can directly impact the performance and reliability of digital signal processing systems.